Cadence
Intern-Design Engineering
💰 CTC / Stipend
N/A Backlogs: N/A Duration (Applicable for internship only): 11 Months Intern + Fte
📊 CGPA Criteria
8
🎓 Eligible Branches
📋 Job Description
Design and develop cycle approximate/Loosly timed C++/SystemC models for Cadence's IPs like PCIe controller, etc for use in early SW development ,architectural exploration and performance analysis at different levels - subsystem and SoC level. - Design and develop protocol specific functional models for various Cadence's interface IPs like PCIe,UCIe,CXL,USB,Ethernet,UFS,DP, etc - Interact with IP designers and architects to understand various IP design/implementation specification and behavior - Participate in defining traffic patterns, tools and methodology based on the model to help identify functional issues and performance bottlenecks - Documentation of design specifications, implementation details, FAQ's, application notes, etc
📝 How to Apply
All interested students must apply on the link below and in description (if any) by 14/03/2026, 08:00 AM.